1. Field of the Invention
The present invention relates to the field of digital multipliers and more specifically to the prediction of a sticky bit.
2. Prior Art
The multiplication of two numbers is a basic arithmetic operation known in mathematics. However, implementing such an operation in a computer or a processor entails the difficulty of using hardware circuitry to provide the product of the two numbers. As processors are reduced to a semiconductor device, i.e. a silicon chip, additional constraints play a role in determining the best scheme for multiplying two numbers. Although various schemes are available to multiply two numbers, one of the most well-known techniques is the use of a tree structure, such as a Wallace Tree, to calculate the product. Additionally, whenever high-precision calculations or calculations involving very large and small numbers are required, processors implement floating-point multiplication for increase performance in arriving at the product.
Typically in a floating-point multiplier, the mantissas of the multiplicand and the multiplier are multiplied using a fast, tree type multiplier to derive the product. Various floating-point standards are available and one of the most well-known is the IEEE (The Institute of Electrical and Electronic Engineers, Inc.) Binary Floating-Point Standard 754. The rounding requirements of this floating-point standard require the use of a round bit and a sticky bit when performing floating-point multiplication. The round bit is defined as the bit of the unrounded mantissa product that is one position less significant than the least significant bit used in the result mantissa. The sticky bit is defined as the OR of all of the bits in the unrounded mantissa product less significant than the round bit. The existing prior art implementations require the calculation of all or part of the mantissa product before the sticky bit can be calculated. That is, once the mantissa product is calculated, then the appropriate bits are OR'ed to determine the sticky bit.
In another faster implementation of the prior art technique, the sticky bit is calculated as the product is calculated in several steps. This prior art technique calculates the lowest few bits of the mantissa product in a first clock cycle and during a second clock cycle, the next few bits of the mantissa product are calculated; and the OR of the mantissa product bits from the first clock cycle is calculated during this second clock cycle. Each additional clock cycle would calculate a few more bits of the mantissa product and OR together the bits of the mantissa calculated in the previous clock cycle. It is not a problem to calculate the sticky bit by this technique because several clock cycles are needed to calculate the product However, even with the implementation of this faster technique, the mantissa product or a portion of the mantissa product still needs to be calculated before the OR'ing to determine the sticky bit can be done.
The disadvantage of the prior art technique is self-evident in that the sticky bit can only be calculated after the calculation of the mantissa product. This adds delay to the processing operation because the rounding operation cannot begin until the sticky bit is known and the sticky bit cannot be determined until the lower half of the mantissa product is known. Therefore, it would be advantageous to develop a scheme in which the sticky bit can be calculated prior to or at the same time that the product is derived. Simply, a parallel processing technique is required to determine the sticky bit while the processor is determining the product of the two mantissas. This will allow a reduction of the delay in the multiplication operation of a processor because the sticky bit will be known when the lower half of the mantissa product is calculated. This technique is especially important as processor speed increases and operations must be performed in less time than the prior art.